MC68HC908GT16 Datasheet, PDF (128/412 Pages) Motorola, Inc – Microcontrollers

Internal Clock Generator (ICG) Module
• Although the clock monitor can be enabled only when both clocks
are stable (ICGS is set or ECGS is set), it will remain set if one of
the clocks goes unstable.
• The clock monitor only works if the external slow (EXTSLOW) bit
in the CONFIG2 register is set to the correct value.
• The internal and external clocks must both be enabled and
running to use the clock monitor.
• When the clock monitor detects inactivity, the inactive clock is
automatically deselected and the active clock selected as the
source for CGMXCLK and TBMCLK. The CMISR can use the
state of the CS bit to check which clock is inactive.
• When the clock monitor detects inactivity, the application may
have been subjected to extreme conditions which may have
affected other circuits. The CMISR should take any appropriate
precautions.
7.5.4 Quantization Error in DCO Output
The digitally controlled oscillator (DCO) is comprised of three major sub-
blocks:
1. Binary weighted divider
2. Variable-delay ring oscillator
3. Ring oscillator fine-adjust circuit
Each of these blocks affects the clock period of the internal clock (ICLK).
Since these blocks are controlled by the digital loop filter (DLF) outputs
DDIV and DSTG, the output of the DCO can change only in quantized
steps as the DLF increments or decrements its output. The following
sections describe how each block will affect the output frequency.
Technical Data
128
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
Internal Clock Generator (ICG) Module
MOTOROLA