MC68HC908GT16 Datasheet, PDF (172/412 Pages) Motorola, Inc – Microcontrollers

Central Processor Unit (CPU)
Table 10-1. Instruction Set Summary (Sheet 5 of 8)
Source
Form
Operation
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
LDHX #opr
LDHX opr
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSL opr,SP
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
MUL
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NEG opr,SP
NOP
NSA
Jump to Subroutine
Load A from M
Load H:X from M
Load X from M
Logical Shift Left
(Same as ASL)
Logical Shift Right
Move
Unsigned multiply
Negate (Two’s Complement)
No Operation
Nibble Swap A
Description
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
A ← (M)
H:X ← (M:M + 1)
X ← (M)
C
b7
0
b0
0
b7
C
b0
(M)_Destination ← (M)_Source
H:X ← (H:X) + 1 (IX+D, DIX+)
X:A ← (X) × (A)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
None
A ← (A[3:0]:A[7:4])
Effect on
CCR
VH I NZC
DIR
EXT
– – – – – – IX2
IX1
IX
IMM
DIR
EXT
0
–
–


–
IX2
IX1
IX
SP1
SP2
0
–
–


–
IMM
DIR
IMM
DIR
EXT
0
–
–


–
IX2
IX1
IX
SP1
SP2
DIR
INH

–
–



INH
IX1
IX
SP1
DIR
INH

–
–
0


INH
IX1
IX
SP1
DD
0
–
–


–
DIX+
IMD
IX+D
– 0 – – – 0 INH
DIR
INH

–
–



INH
IX1
IX
SP1
– – – – – – INH
– – – – – – INH
BD dd 4
CD hh ll 5
DD ee ff 6
ED ff
5
FD
4
A6 ii
2
B6 dd 3
C6 hh ll 4
D6 ee ff 4
E6 ff
3
F6
2
9EE6 ff
4
9ED6 ee ff 5
45 ii jj 3
55 dd 4
AE ii
2
BE dd 3
CE hh ll 4
DE ee ff 4
EE ff
3
FE
2
9EEE ff
4
9EDE ee ff 5
38 dd 4
48
1
58
1
68 ff
4
78
3
9E68 ff
5
34 dd 4
44
1
54
1
64 ff
4
74
3
9E64 ff
5
4E dd dd 5
5E dd 4
6E ii dd 4
7E dd 4
42
5
30 dd 4
40
1
50
1
60 ff
4
70
3
9E60 ff
5
9D
1
62
3
Technical Data
172
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
Central Processor Unit (CPU)
MOTOROLA