MC68HC908GT16 Datasheet, PDF (73/412 Pages) Motorola, Inc – Microcontrollers

Resets and Interrupts
Resets
All internal reset sources pull the RST pin low for 32 CGMXCLK cycles
to allow resetting of external devices. The MCU is held in reset for an
additional 32 CGMXCLK cycles after releasing the RST pin.
RST PIN
CGMXCLK
INTERNAL
RESET
PULLED LOW BY MCU
32 CYCLES
32 CYCLES
Figure 4-1. Internal Reset Timing
4.3.3.1 Power-On Reset (POR)
A power-on reset (POR) is an internal reset caused by a positive
transition on the V_DD pin. V_DD at the POR must go completely to 0 V to
reset the MCU. This distinguishes between a reset and a POR. The POR
is not a brown-out detector, low-voltage detector, or glitch detector.
A power-on reset:
• Holds the clocks to the CPU and modules inactive for an oscillator
stabilization delay of 4096 CGMXCLK cycles
• Drives the RST pin low during the oscillator stabilization delay
• Releases the RST pin 32 CGMXCLK cycles after the oscillator
stabilization delay
• Releases the CPU to begin the reset vector sequence 64
CGMXCLK cycles after the oscillator stabilization delay
• Sets the POR and LP bits in the SIM reset status register and
clears all other bits in the register
4.3.3.2 Computer Operating Properly (COP) Reset
A COP reset is an internal reset caused by an overflow of the COP
counter. A COP reset sets the COP bit in the system integration module
(SIM) reset status register.
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
MOTOROLA
Resets and Interrupts
Technical Data
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