MC68HC908GT16 Datasheet, PDF (63/412 Pages) Motorola, Inc – Microcontrollers

3.6 Internal Clock Generator Module (ICG)
Low-Power Modes
Internal Clock Generator Module (ICG)
3.6.1 Wait Mode
The internal clock generator (ICG) module remains active in wait mode.
If enabled, the ICG interrupt to the CPU can bring the MCU out of wait
mode.
In some applications, low power-consumption is desired in wait mode
and a high-frequency clock is not needed. In these applications, reduce
power consumption by either selecting a low-frequency external clock
and turn the internal clock generator off or reduce the bus frequency by
minimizing the ICG multiplier factor (N) before executing the WAIT
instruction.
3.6.2 Stop Mode
The value of the oscillator enable in stop (OSCENINSTOP) bit in the
CONFIG2 register determines the behavior of the ICG in stop mode. If
OSCENINSTOP is low, the ICG is disabled in stop and, upon execution
of the STOP instruction, all ICG activity will cease and the output clocks
(CGMXCLK, CGMOUT, COPCLK, and TBMCLK) will be held low.
Power consumption will be minimal.
If OSCENINSTOP is high, the ICG is enabled in stop and activity will
continue. This is useful if the timebase module (TBM) is required to bring
the MCU out of stop mode. ICG interrupts will not bring the MCU out of
stop mode in this case.
During stop mode, if OSCENINSTOP is low, several functions in the ICG
are affected. The stable bits (ECGS and ICGS) are cleared, which will
enable the external clock stabilization divider upon recovery. The clock
monitor is disabled (CMON = 0) which will also clear the clock monitor
interrupt enable (CMIE) and clock monitor flag (CMF) bits. The CS,
ICGON, ECGON, N, TRIM, DDIV, and DSTG bits are unaffected.
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
MOTOROLA
Low-Power Modes
Technical Data
63