MC68HC908GT16 Datasheet, PDF (212/412 Pages) Motorola, Inc – Microcontrollers

Monitor ROM (MON)
RST
0.1 µF
N.C.
OSC2
1 µF
1 µF
DB9
2
3
4 _C1+
+
5 _C1–
4 _C2+
+
5 _C2–
7
8
MAX232
V_DD
16
9.8304 MHz CLOCK
OSC1
15
V+ ²
V– ⁶
1 µF
10
9
0.1 µF
V_TST
+
V_DD
+
10 kΩ
74HC125
6
5
74HC125
2
3
4
1 kΩ
9.1 V
IRQ
PTA0
5
1
V_DDA
V_DD
0.1 µF
PTC0
PTC3
V_DD
10 kΩ
10 kΩ
2 kΩ
PTC1
V_SS
V_SSA
Figure 15-3. Standard Monitor Mode
The monitor code has been updated from previous versions of the
monitor code to allow the ICG to generate the internal clock. This option,
which is selected when IRQ is held low out of reset, is intended to
support serial communication/ programming at 9600 baud in monitor
mode by using the ICG, and the ICG user trim value ICGTR5 (if
programmed) to generate the desired internal frequency (2.4576 MHz).
If ICGTR5 is not programmed (i.e., the value is $FF) then the ICG will
operate at a nominal (untrimmed) 2.45 MHz and communications will be
nominally at 9600 baud but the untrimmed rate may cause difficulties
with hosts which cannot automatically adjust their data rates to match.
Since this feature is enabled only when IRQ is held low out of reset, it
cannot be used when the reset vector is programmed (i.e., the value is
not $FFFF) because entry into monitor mode in this case requires V_TST
on IRQ.
Technical Data
212
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
Monitor ROM (MON)
MOTOROLA