MC68HC908GT16 Datasheet, PDF (231/412 Pages) Motorola, Inc – Microcontrollers

READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
WRITE PTA ($0000)
DDRAx
PTAx
Input/Output (I/O) Ports
Port A
V_DD
PTAPUEx
45 k
PTAx
READ PTA ($0000)
Figure 16-4. Port A I/O Circuit
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx
data latch. When bit DDRAx is a logic 0, reading address $0000 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 16-2 summarizes
the operation of the port A pins.
Table 16-2. Port A Pin Functions
PTAPUE
Bit
DDRA PTA
Bit
Bit
I/O Pin
Mode
Accesses
to DDRA
Read/Write
1
0
X⁽¹⁾
Input, V_DD(2)
DDRA7–DDRA0
0
0
X
Input, Hi-Z⁽⁴⁾
DDRA7–DDRA0
X
1
X
Output
DDRA7–DDRA0
1. X = Don’t care
2. I/O pin pulled up to V_DD by internal pullup device
3. Writing affects data register, but does not affect input.
4. Hi-Z = High impedance
Accesses
to PTA
Read
Write
Pin
PTA7–PTA0⁽³⁾
Pin
PTA7–PTA0⁽³⁾
PTA7–PTA0
PTA7–PTA0
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
MOTOROLA
Input/Output (I/O) Ports
Technical Data
231