MC68HC908GT16 Datasheet, PDF (292/412 Pages) Motorola, Inc – Microcontrollers

Enhanced Serial Communications Interface (ESCI)
18.10.2 ESCI Arbiter Data Register
Address: $000B
Bit 7
6
5
4
3
2
1
Read: ARD7 ARD6 ARD5 ARD4 ARD3 ARD2 ARD1
Write:
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 18-19. ESCI Arbiter Data Register (SCIADAT)
Bit 0
ARD0
0
ARD7–ARD0 — Arbiter Least Significant Counter Bits
These read-only bits are the eight LSBs of the
9-bit arbiter counter. Clear ARD7–ARD0 by writing any value to
SCIACTL. Writing logic 0s to AM1 and AM0 permanently resets the
counter and keeps it in this idle state. Reset clears ARD7–ARD0.
18.10.3 Bit Time Measurement
Two bit time measurement modes, described here, are available
according to the state of ACLK.
1. ACLK = 0 — The counter is clocked with one half of the bus clock.
The counter is started when a falling edge on the RxD pin is
detected. The counter will be stopped on the next falling edge.
ARUN is set while the counter is running, AFIN is set on the
second falling edge on RxD (for instance, the counter is stopped).
This mode is used to recover the received baud rate.
See Figure 18-20.
2. ACLK = 1 — The counter is clocked with one half of the ESCI input
clock generated by the ESCI prescaler. The counter is started
when a logic 0 is detected on RxD (see Figure 18-21). A logic 0
on RxD on enabling the bit time measurement with ACLK = 1
leads to immediate start of the counter (see Figure 18-22). The
counter will be stopped on the next rising edge of RxD. This mode
is used to measure the length of a received break.
Technical Data
292
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
Enhanced Serial Communications Interface (ESCI) Module
MOTOROLA