MC68HC908GT16 Datasheet, PDF (193/412 Pages) Motorola, Inc – Microcontrollers

External Interrupt (IRQ)
IRQ Module During Break Interrupts
12.6 IRQ Module During Break Interrupts
The BCFE bit in the SIM break flag control register (SBFCR) enables
software to clear the latch during the break state. See Section 6. Break
Module (BRK).
To allow software to clear the IRQ latch during a break interrupt, write a
logic 1 to the BCFE bit. If a latch is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect CPU interrupt flags during the break state, write a logic 0 to
the BCFE bit. With BCFE at logic 0 (its default state), writing to the ACK
bit in the IRQ status and control register during the break state has no
effect on the IRQ interrupt flags.
12.7 IRQ Status and Control Register
The IRQ status and control register (INTSCR) controls and monitors
operation of the IRQ module. The INTSCR:
• Shows the state of the IRQ flag
• Clears the IRQ latch
• Masks IRQ interrupt request
• Controls triggering sensitivity of the IRQ1 interrupt pin
Address: $001D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
IRQF
0
IMASK MODE
ACK
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-3. IRQ Status and Control Register (INTSCR)
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
MOTOROLA
External Interrupt (IRQ)
Technical Data
193