MC68HC908GT16 Datasheet, PDF (263/412 Pages) Motorola, Inc – Microcontrollers

Enhanced Serial Communications Interface (ESCI) Module
Functional Description
After a complete character shifts into the receive shift register, the data
portion of the character transfers to the SCDR. The ESCI receiver full bit,
SCRF, in ESCI status register 1 (SCS1) becomes set, indicating that the
received byte can be read. If the ESCI receive interrupt enable bit,
SCRIE, in SCC2 is also set, the SCRF bit generates a receiver CPU
interrupt request.
18.5.3.3 Data Sampling
The receiver samples the RxD pin at the RT clock rate. The RT clock is
an internal signal with a frequency 16 times the baud rate. To adjust for
baud rate mismatch, the RT clock is resynchronized at these times (see
Figure 18-6):
• After every start bit
• After the receiver detects a data bit change from logic 1 to logic 0
(after the majority of data bit samples at RT8, RT9, and RT10
returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
To locate the start bit, data recovery logic does an asynchronous search
for a logic 0 preceded by three logic 1s. When the falling edge of a
possible start bit occurs, the RT clock begins to count to 16.
START BIT
LSB
RxD
SAMPLES
RT
CLOCK
RT CLOCK
STATE
RT CLOCK
RESET
START BIT
START BIT
DATA
QUALIFICATION VERIFICATION SAMPLING
Figure 18-6. Receiver Data Sampling
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
MOTOROLA
Enhanced Serial Communications Interface (ESCI) Module
Technical Data
263