MC68HC908GT16 Datasheet, PDF (62/412 Pages) Motorola, Inc – Microcontrollers

Low-Power Modes
3.4.2 Stop Mode
The break module is inactive in stop mode. A break interrupt causes exit
from stop mode and sets the SBSW bit in the break status register. The
STOP instruction does not affect break module register states.
3.5 Central Processor Unit (CPU)
3.5.1 Wait Mode
The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from wait mode by interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
3.5.2 Stop Mode
The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
Technical Data
62
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
Low-Power Modes
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