MC68HC908GT16 Datasheet, PDF (133/412 Pages) Motorola, Inc – Microcontrollers

Internal Clock Generator (ICG) Module
Usage Notes
from half speed to quarter speed takes 88*N*τ_ICLKFAST; going from
quarter speed to eighth speed takes 176*N*τ_ICLKFAST; and so on. This
series can be expressed as (2^x–1)*44*N*τ_ICLKFAST, where x is the
number of times the speed needs doubled or halved. Since 2^x happens
to be equal to τ_ICLKSLOW/τ_ICLKFAST, the equation reduces to
44*N*(τ_ICLKSLOW–τ_ICLKFAST).
Note that increasing speed takes much longer than decreasing speed
since N is higher. This can be expressed in terms of the initial clock
period (τ₁) minus the final clock period (τ₂) as such:
τ₁₅ = abs[44N(τ₁ – τ₂)]
7.5.6.2 Settling to Within 5 Percent
Once the clock period is within 15 percent of the desired clock period,
the filter starts making smaller adjustments. When between 15 percent
and 5 percent error, each correction will adjust the clock period between
1.61 percent and 2.94 percent. In this mode, a maximum of eight
corrections will be required to get to less than 5 percent error. Since the
clock period is relatively close to desired, each correction takes
approximately the same period of time, or 4*τ_IBASE. At this point, the
internal clock stable bit (ICGS) will be set and the clock frequency is
usable, although the error will be as high as 5 percent. The total time to
this point is:
τ₅ = abs[44N(τ₁ – τ₂)] + 32τ_IBASE
7.5.6.3 Total Settling Time
Once the clock period is within 5 percent of the desired clock period, the
filter starts making minimum adjustments. In this mode, each correction
will adjust the frequency between 0.202 percent and 0.368 percent. A
maximum of 24 corrections will be required to get to the minimum error.
Each correction takes approximately the same period of time, or
4*τ_IBASE. Added to the corrections for 15 percent to 5 percent, this
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
MOTOROLA
Internal Clock Generator (ICG) Module
Technical Data
133