MC68HC908GT16 Datasheet, PDF (107/412 Pages) Motorola, Inc – Microcontrollers

Break Module (BRK)
Break Module Registers
6.6.3 Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a
break caused an exit from stop or wait mode. The flag is useful in
applications requiring a return to stop or wait mode after exiting from a
break interrupt.
Address: $FE00
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
1
0
0
SBSW
0
Write: R
R
R
R
R
R
NOTE
R
Reset: 0
0
0
1
0
0
0
0
Note: Writing a logic 0 clears SBSW.
R = Reserved
Figure 6-6. SIM Break Status Register (SBSR)
SBSW — SIM Break Stop/Wait Bit
This read/write bit is set when a break interrupt causes an exit from
stop or wait mode. Clear SBSW by writing a logic 0 to it. Reset clears
SBSW.
1 = Break interrupt during stop/wait mode
0 = No break interrupt during stop/wait mode
SBSW can be read within the break interrupt routine. The user can
modify the return address on the stack by subtracting 1 from it. The
following code is an example.
This code works if the H register was stacked in the break interrupt
routine. Execute this code at the end of the break interrupt routine.
HIBYTE EQU 5
LOBYTE EQU 6
;
If not SBSW, do RTI
BRCLR SBSW,BSR, RETURN ; See if wait mode or stop mode
; was exited by break.
TST LOBYTE,SP
; If RETURNLO is not 0,
BNE DOLO
; then just decrement low byte.
DEC HIBYTE,SP
; Else deal with high byte also.
DOLO DEC LOBYTE,SP
; Point to WAIT/STOP opcode.
RETURN PULH
; Restore H register.
RTI
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
MOTOROLA
Break Module (BRK)
Technical Data
107