MC68HC908GT16 Datasheet, PDF (271/412 Pages) Motorola, Inc – Microcontrollers

Enhanced Serial Communications Interface (ESCI) Module
I/O Signals
does the first step on such a bit before the break, the bit cannot change
during the break state as long as BCFE is at logic 0. After the break,
doing the second step clears the status bit.
18.8 I/O Signals
Port E shares two of its pins with the ESCI module. The two ESCI I/O
pins are:
• PTE0/TxD — transmit data
• PTE1/RxD — receive data
18.8.1 PTE0/TxD (Transmit Data)
The PTE0/TxD pin is the serial data output from the ESCI transmitter.
The ESCI shares the PTE0/TxD pin with port E. When the ESCI is
enabled, the PTE0/TxD pin is an output regardless of the state of the
DDRE0 bit in data direction register E (DDRE).
18.8.2 PTE1/RxD (Receive Data)
The PTE1/RxD pin is the serial data input to the ESCI receiver. The
ESCI shares the PTE1/RxD pin with port E. When the ESCI is enabled,
the PTE1/RxD pin is an input regardless of the state of the DDRE1 bit in
data direction register E (DDRE).
18.9 I/O Registers
These I/O registers control and monitor ESCI operation:
• ESCI control register 1, SCC1
• ESCI control register 2, SCC2
• ESCI control register 3, SCC3
• ESCI status register 1, SCS1
• ESCI status register 2, SCS2
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
MOTOROLA
Enhanced Serial Communications Interface (ESCI) Module
Technical Data
271