MC68HC908GT16 Datasheet, PDF (207/412 Pages) Motorola, Inc – Microcontrollers

Low-Voltage Inhibit (LVI)
LVI Status Register
14.5 LVI Status Register
The LVI status register (LVISR) indicates if the V_DD voltage was
detected below the V_TRIPF level.
Address: $FE0C
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
0
0
0
0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-3. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V_DD voltage falls below the
V_TRIPF trip voltage (see Table 14-1). Reset clears the LVIOUT bit.
Table 14-1. LVIOUT Bit Indication
V_DD
V_DD > V_TRIPR
V_DD < V_TRIPF
V_TRIPF < V_DD < V_TRIPR
LVIOUT
0
1
Previous value
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
MOTOROLA
Low-Voltage Inhibit (LVI)
Technical Data
207