MC68HC908GT16 Datasheet, PDF (260/412 Pages) Motorola, Inc – Microcontrollers

Enhanced Serial Communications Interface (ESCI)
Receiving a break character has these effects on ESCI registers:
• Sets the framing error bit (FE) in SCS1
• Sets the ESCI receiver full bit (SCRF) in SCS1
• Clears the ESCI data register (SCDR)
• Clears the R8 bit in SCC3
• Sets the break flag bit (BKF) in SCS2
• May set the overrun (OR), noise flag (NF), parity error (PE),
or reception in progress flag (RPF) bits
18.5.2.4 Idle Characters
For TXINV = 0 (output not inverted), a transmitted idle character
contains all logic 1s and has no start, stop, or parity bit. Idle character
length depends on the M bit in SCC1. The preamble is a synchronizing
idle character that begins every transmission.
If the TE bit is cleared during a transmission, the TxD pin becomes idle
after completion of the transmission in progress. Clearing and then
setting the TE bit during a transmission queues an idle character to be
sent after the character currently being transmitted.
NOTE:
When queueing an idle character, return the TE bit to logic 1 before the
stop bit of the current character shifts out to the TxD pin. Setting TE after
the stop bit appears on TxD causes data previously written to the SCDR
to be lost. A good time to toggle the TE bit for a queued idle character is
when the SCTE bit becomes set and just before writing the next byte to
the SCDR.
18.5.2.5 Inversion of Transmitted Output
The transmit inversion bit (TXINV) in ESCI control register 1 (SCC1)
reverses the polarity of transmitted data. All transmitted values including
idle, break, start, and stop bits, are inverted when TXINV is at logic 1.
See 18.9.1 ESCI Control Register 1.
Technical Data
260
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
Enhanced Serial Communications Interface (ESCI) Module
MOTOROLA