MC68HC908GT16 Datasheet, PDF (246/412 Pages) Motorola, Inc – Microcontrollers

Input/Output (I/O) Ports
ICG registers. PTE4 will become an external input clock source,
OSC1, if selected in the configuration registers and enabled in the
ICG registers. See Section 7. Internal Clock Generator (ICG)
Module and Section 9. Computer Operating Properly (COP)
Module. While configured as oscillator pins, writes have no effect and
reads return undefined values.
RxD — SCI Receive Data Input
The PTE1/RxD pin is the receive data input for the SCI module.
When the enable SCI bit, ENSCI, is clear, the SCI module is disabled,
and the PTE1/RxD pin is available for general-purpose I/O. See
Section 18. Enhanced Serial Communications Interface (ESCI)
Module.
TxD — SCI Transmit Data Output
The PTE0/TxD pin is the transmit data output for the SCI module.
When the enable SCI bit, ENSCI, is clear, the SCI module is disabled,
and the PTE0/TxD pin is available for general-purpose I/O. See
Section 18. Enhanced Serial Communications Interface (ESCI)
Module.
16.7.2 Data Direction Register E
Data direction register E (DDRE) determines whether each port E pin is
an input or an output. Writing a logic 1 to a DDRE bit enables the output
buffer for the corresponding port E pin; a logic 0 disables the output
buffer.
Address: $000C
Bit 7
6
5
4
3
2
1
Read: 0
0
0
DDRE4 DDRE3 DDRE2 DDRE1
Write:
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 16-18. Data Direction Register E (DDRE)
Bit 0
DDRE0
0
Technical Data
246
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
Input/Output (I/O) Ports
MOTOROLA