MC68HC908GT16 Datasheet, PDF (283/412 Pages) Motorola, Inc – Microcontrollers

Enhanced Serial Communications Interface (ESCI) Module
I/O Registers
18.9.5 ESCI Status Register 2
ESCI status register 2 (SCS2) contains flags to signal these conditions:
• Break character detected
• Incoming data
Address: $0017
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
0
0
BKF
RPF
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 18-14. ESCI Status Register 2 (SCS2)
BKF — Break Flag Bit
This clearable, read-only bit is set when the ESCI detects a break
character on the RxD pin. In SCS1, the FE and SCRF bits are also
set. In 9-bit character transmissions, the R8 bit in SCC3 is cleared.
BKF does not generate a CPU interrupt request. Clear BKF by
reading SCS2 with BKF set and then reading the SCDR. Once
cleared, BKF can become set again only after logic 1s again appear
on the RxD pin followed by another break character. Reset clears the
BKF bit.
1 = Break character detected
0 = No break character detected
RPF — Reception in Progress Flag Bit
This read-only bit is set when the receiver detects a logic 0 during the
RT1 time period of the start bit search. RPF does not generate an
interrupt request. RPF is reset after the receiver detects false start bits
(usually from noise or a baud rate mismatch), or when the receiver
detects an idle character. Polling RPF before disabling the ESCI
module or entering stop mode can show whether a reception is in
progress.
1 = Reception in progress
0 = No reception in progress
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
MOTOROLA
Enhanced Serial Communications Interface (ESCI) Module
Technical Data
283