MC68HC908GT16 Datasheet, PDF (155/412 Pages) Motorola, Inc – Microcontrollers

Computer Operating Properly (COP) Module
I/O Signals
The COP counter is a free-running 6-bit counter preceded by a 12-bit
prescaler counter. If not cleared by software, the COP counter overflows
and generates an asynchronous reset after 2¹⁸ – 2⁴ or 2¹³ – 2⁴
COPCLK cycles, depending on the state of the COP rate select bit,
COPRS, in the configuration register. With a 2¹³ – 2⁴ COPCLK cycle
overflow option, a 32.768-kHz crystal gives a COP timeout period of
250 ms. Writing any value to location $FFFF before an overflow occurs
prevents a COP reset by clearing the COP counter and stages 12
through 5 of the prescaler.
NOTE:
Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
A COP reset pulls the RST pin low for 32 COPCLK cycles and sets the
COP bit in the reset status register (RSR).
NOTE:
In monitor mode, the COP is disabled if the RST pin or the IRQ1 is held
at V_TST. During the break state, V_TST on the RST pin disables the COP.
Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
9.4 I/O Signals
The following paragraphs describe the signals shown in Figure 9-1.
9.4.1 COPCLK
COPCLK is a clock generated by the clock selection circuit in the internal
clock generator (ICG). See 7.4.5 Clock Selection Circuit for more
details.
9.4.2 STOP Instruction
The STOP instruction clears the COP prescaler.
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
MOTOROLA
Computer Operating Properly (COP) Module
Technical Data
155