 English |
|
|
|
|
|
|
|
| MC68HC908GT16 Datasheet, PDF (214/412 Pages) Motorola, Inc – Microcontrollers | |||
| |||
| ◁ |
Table 15-1. Monitor Mode Signal Requirements and Options
IRQ RESET
$FFFE/
$FFFF
ICG
PTC0
PTC1
PTC3
External
Clock
CGMOUT
Bus
Frequency
COP
For Serial
Communication
PTA0
Baud
Rate
Comment
X GND
X
XX
X
X
X
0
0
Disabled X
0
No operation until
reset goes high
VTST VDD
X
OFF 1
0
0
4.9152
MHz
4.9152
MHz
2.4576
MHz
Disabled
1
9600
PTC3 determines
frequency
divider
VTST VDD
X
OFF 1
0
1
9.8304
MHz
4.9152
MHz
2.4576
MHz
Disabled
1
9600
PTC3 determines
frequency
divider
External
VDD VDD
$FF
(blank)
OFF
X
X
X
9.8304
MHz
4.9152
MHz
2.4576
MHz
Disabled
1
9600
frequency
always
divided by 4
GND VDD
$FF
(blank)
ON
X
X
X
X
Nominal
4.91 MHz
Nominal
2.45 MHz
Disabled
1
Nominal
9600
ICG enabled
VDD
or
VDD
$FF
(blank)
OFF
X
X
X
X
â
GND
â
Enabled X
Enters user
mode â will
â
encounter an
illegal address
reset
VDD
or
Not
VDD
$FF
(program-
ON
X
X
X
GND
med)
X
Nominal
3.2 MHz
Nominal
1.6 MHz
Enabled
X
â Enters user mode
Note: X = donât care
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese