MC68HC908GT16 Datasheet, PDF (191/412 Pages) Motorola, Inc – Microcontrollers

External Interrupt (IRQ)
Functional Description
The external interrupt pin is falling-edge triggered and is software-
configurable to be either falling-edge or falling-edge and low-level
triggered. The MODE bit in the INTSCR controls the triggering sensitivity
of the IRQ1 pin.
When an interrupt pin is edge-triggered only, the interrupt remains set
until a vector fetch, software clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level triggered, the
interrupt remains set until both of these events occur:
• Vector fetch or software clear
• Return of the interrupt pin to logic 1
The vector fetch or software clear may occur before or after the interrupt
pin returns to logic 1. As long as the pin is low, the interrupt request
remains pending. A reset will clear the latch and the MODE control bit,
thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the INTSCR mask all external interrupt
requests. A latched interrupt request is not presented to the interrupt
priority logic unless the IMASK bit is clear.
NOTE: The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
Addr.
$001D
Register Name
Bit 7
6
5
Read: 0
0
0
IRQ Status and Control
Register (INTSCR) Write:
See page 193.
Reset: 0
0
0
= Unimplemented
4
3
0
IRQF
0
0
Figure 12-2. IRQ I/O Register Summary
2
1
Bit 0
0
IMASK MODE
ACK
0
0
0
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
MOTOROLA
External Interrupt (IRQ)
Technical Data
191