MC68HC908GT16 Datasheet, PDF (135/412 Pages) Motorola, Inc – Microcontrollers

Internal Clock Generator (ICG) Module
Low-Power Modes
output frequency by about ±0.195 percent of the unadjusted frequency
(adding to TRIM will decrease frequency). Therefore, the frequency of
IBASE can be changed to ±25 percent of its unadjusted value, which is
enough to cancel the process variability mentioned before.
The best way to trim the internal clock is to use the timer to measure the
width of an input pulse on an input capture pin (this pulse must be
supplied by the application and should be as long or wide as possible).
Considering the prescale value of the timer and the theoretical (zero
error) frequency of the bus (307.2 kHz *N/4), the error can be calculated.
This error, expressed as a percentage, can be divided by 0.195 percent
and the resultant factor added or subtracted from TRIM. This process
should be repeated to eliminate any residual error.
7.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
7.6.1 Wait Mode
The ICG remains active in wait mode. If enabled, the ICG interrupt to the
CPU can bring the MCU out of wait mode.
In some applications, low power-consumption is desired in wait mode
and a high-frequency clock is not needed. In these applications, reduce
power consumption by either selecting a low-frequency external clock
and turn the internal clock generator off or reduce the bus frequency by
minimizing the ICG multiplier factor (N) before executing the WAIT
instruction.
7.6.2 Stop Mode
The value of the oscillator enable in stop (OSCENINSTOP) bit in the
CONFIG2 register determines the behavior of the ICG in stop mode. If
OSCENINSTOP is low, the ICG is disabled in stop and, upon execution
of the STOP instruction, all ICG activity will cease and the output clocks
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
MOTOROLA
Internal Clock Generator (ICG) Module
Technical Data
135