MC68HC908GT16 Datasheet, PDF (261/412 Pages) Motorola, Inc – Microcontrollers

Enhanced Serial Communications Interface (ESCI) Module
Functional Description
18.5.2.6 Transmitter Interrupts
These conditions can generate CPU interrupt requests from the ESCI
transmitter:
• ESCI transmitter empty (SCTE) — The SCTE bit in SCS1
indicates that the SCDR has transferred a character to the
transmit shift register. SCTE can generate a transmitter CPU
interrupt request. Setting the ESCI transmit interrupt enable bit,
SCTIE, in SCC2 enables the SCTE bit to generate transmitter
CPU interrupt requests.
• Transmission complete (TC) — The TC bit in SCS1 indicates that
the transmit shift register and the SCDR are empty and that no
break or idle character has been generated. The transmission
complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to
generate transmitter CPU interrupt requests.
18.5.3 Receiver
Figure 18-5 shows the structure of the ESCI receiver. The receiver I/O
registers are summarized in Figure 18-2.
18.5.3.1 Character Length
The receiver can accommodate either 8-bit or 9-bit data. The state of the
M bit in ESCI control register 1 (SCC1) determines character length.
When receiving 9-bit data, bit R8 in ESCI control register 3 (SCC3) is the
ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth
bit (bit 7).
18.5.3.2 Character Reception
During an ESCI reception, the receive shift register shifts characters in
from the RxD pin. The ESCI data register (SCDR) is the read-only buffer
between the internal data bus and the receive shift register.
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
MOTOROLA
Enhanced Serial Communications Interface (ESCI) Module
Technical Data
261