MC68HC908GT16 Datasheet, PDF (157/412 Pages) Motorola, Inc – Microcontrollers

Computer Operating Properly (COP) Module
COP Control Register
9.5 COP Control Register
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address: $FFFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Low byte of reset vector
Write:
Clear COP counter
Reset:
Unaffected by reset
Figure 9-2. COP Control Register (COPCTL)
9.6 Interrupts
The COP does not generate central processor unit (CPU) interrupt
requests.
9.7 Monitor Mode
When monitor mode is entered with V_TST on the IRQ pin, the COP is
disabled as long as V_TST remains on the IRQ pin or the RST pin. When
monitor mode is entered by having blank reset vectors and not having
V_TST on the IRQ pin, the COP is automatically disabled until a POR
occurs.
9.8 Low-Power Modes
The WAIT and STOP instructions put the microcontroller unit (MCU) in
low power-consumption standby modes.
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
MOTOROLA
Computer Operating Properly (COP) Module
Technical Data
157