MC68HC908GT16 Datasheet, PDF (151/412 Pages) Motorola, Inc – Microcontrollers

Configuration Register (CONFIG)
Functional Description
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the
LVI to operate during stop mode. Reset clears LVISTOP.
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module.
See Section 14. Low-Voltage Inhibit (LVI).
1 = LVI module resets disabled
0 = LVI module resets enabled
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module. See Section 14. Low-Voltage
Inhibit (LVI).
1 = LVI module power disabled
0 = LVI module power enabled
LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit
LVI5OR3 selects the voltage operating mode of the LVI module. See
Section 14. Low-Voltage Inhibit (LVI) The voltage mode selected
for the LVI should match the operating V_DD. See Section 23.
Electrical Specifications for the LVI’s voltage trip points for each of
the modes.
1 = LVI operates in 5-V mode.
0 = LVI operates in 3-V mode.
NOTE: The LVI5OR3 bit is cleared by a power-on reset (POR) only. Other
resets will leave this bit unaffected.
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32
CGMXCLK cycles instead of a 4096-CGMXCLK cycle delay.
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLCK cycles
NOTE: Exiting stop mode by an LVI reset will result in the long stop recovery.
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
MOTOROLA
Configuration Register (CONFIG)
Technical Data
151