MC68HC908GT16 Datasheet, PDF (132/412 Pages) Motorola, Inc – Microcontrollers

Internal Clock Generator (ICG) Module
• Switch back to internal (see 7.5.1 Switching Clock Sources), if
desired.
• Turn on the clock monitor (see 7.5.2 Enabling the Clock
Monitor), if desired.
7.5.6 Nominal Frequency Settling Time
Because the clock period of the internal clock (ICLK) is dependent on the
digital loop filter outputs (DDIV and DSTG) which cannot change
instantaneously, ICLK temporarily will operate at an incorrect clock
period when any operating condition changes. This happens whenever
the part is reset, the ICG multiply factor (N) is changed, the ICG trim
factor (TRIM) is changed, or the internal clock is enabled after inactivity
(stop mode or disabled operation). The time that the ICLK takes to adjust
to the correct period is known as the settling time.
Settling time depends primarily on how many corrections it takes to
change the clock period and the period of each correction. Since the
corrections require four periods of the low-frequency base clock
(4*τ_IBASE), and since ICLK is N (the ICG multiply factor for the desired
frequency) times faster than IBASE, each correction takes 4*N*τ_ICLK.
The period of ICLK, however, will vary as the corrections occur.
7.5.6.1 Settling to Within 15 Percent
When the error is greater than 15 percent, the filter takes eight
corrections to double or halve the clock period. Due to how the DCO
increases or decreases the clock period, the total period of these eight
corrections is approximately 11 times the period of the fastest correction.
(If the corrections were perfectly linear, the total period would be 11.5
times the minimum period; however, the ring must be slightly nonlinear.)
Therefore, the total time it takes to double or halve the clock period is
44*N*τ_ICLKFAST.
If the clock period needs more than doubled or halved, the same
relationship applies, only for each time the clock period needs doubled,
the total number of cycles doubles. That is, when transitioning from fast
to slow, going from the initial speed to half speed takes 44*N*τ_ICLKFAST;
Technical Data
132
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
Internal Clock Generator (ICG) Module
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