MC68HC908GT16 Datasheet, PDF (61/412 Pages) Motorola, Inc – Microcontrollers

3.2.2 Stop Mode
Low-Power Modes
Analog-to-Digital Converter (ADC)
Stop mode is entered when a STOP instruction is executed. The CPU
clock is disabled and the bus clock is disabled if the OSCENINSTOP bit
in the CONFIG2 register is at a logic 0. (See Section 8. Configuration
Register (CONFIG).)
3.3 Analog-to-Digital Converter (ADC)
3.3.1 Wait Mode
The analog-to-digital converter (ADC) continues normal operation
during wait mode. Any enabled CPU interrupt request from the ADC can
bring the MCU out of wait mode. If the ADC is not required to bring the
MCU out of wait mode, power down the ADC by setting ADCH4–ADCH0
bits in the ADC status and control register before executing the WAIT
instruction.
3.3.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction.
Any pending conversion is aborted. ADC conversions resume when the
MCU exits stop mode after an external interrupt. Allow one conversion
cycle to stabilize the analog circuitry.
3.4 Break Module (BRK)
3.4.1 Wait Mode
If enabled, the break (BRK) module is active in wait mode. In the break
routine, the user can subtract one from the return address on the stack
if the SBSW bit in the break status register is set.
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
MOTOROLA
Low-Power Modes
Technical Data
61