MC68HC908GT16 Datasheet, PDF (74/412 Pages) Motorola, Inc – Microcontrollers

Resets and Interrupts
OSC1
PORRST⁽¹⁾
CGMXCLK
4096
32
32
CYCLES CYCLES CYCLES
CGMOUT
RST PIN
INTERNAL
RESET
1. PORRST is an internally generated power-on reset pulse.
Figure 4-2. Power-On Reset Recovery
To clear the COP counter and prevent a COP reset, write any value to
the COP control register at location $FFFF.
4.3.3.3 Low-Voltage Inhibit Reset
A low-voltage inhibit (LVI) reset is an internal reset caused by a drop in
the power supply voltage to the LVI_TRIPF voltage.
An LVI reset:
• Holds the clocks to the CPU and modules inactive for an oscillator
stabilization delay of 4096 CGMXCLK cycles after the power
supply voltage rises to the LVI_TRIPR voltage
• Drives the RST pin low for as long as V_DD is below the LVI_TRIPR
voltage and during the oscillator stabilization delay
• Releases the RST pin 32 CGMXCLK cycles after the oscillator
stabilization delay
• Releases the CPU to begin the reset vector sequence
64 CGMXCLK cycles after the oscillator stabilization delay
• Sets the LVI bit in the SIM reset status register
Technical Data
74
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
Resets and Interrupts
MOTOROLA