MC68HC908GT16 Datasheet, PDF (299/412 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
SIM Bus Clock Control and Generation
19.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in Figure 19-3. This clock
originates from either an external oscillator or from the internal clock
generator.
ECLK
ICLK
ICG
GENERATOR
SELECT
CIRCUIT
CS
COPCLK
TBMCLK
CGMXCLK
A
CGMOUT
÷2
B _S*
*WHEN S = 1,
CGMOUT = B
MONITOR MODE
USER MODE
ICG
COP PRESCALER
TBM PRESCALER
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIM
Figure 19-3. System Clock Signals
19.3.1 Bus Timing
In user mode, the internal bus frequency is the internal clock generator
output (CGMXCLK) divided by four.
19.3.2 Clock Startup from POR or LVI Reset
When the power-on reset module or the low-voltage inhibit module
generates a reset, the clocks to the CPU and peripherals are inactive
and held in an inactive phase until after the 4096 CGMXCLK cycle POR
timeout has completed. The RST pin is driven low by the SIM during this
entire period. The IBUS clocks start upon completion of the timeout.
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
MOTOROLA
System Integration Module (SIM)
Technical Data
299