MC68HC908GT16 Datasheet, PDF (81/412 Pages) Motorola, Inc – Microcontrollers

Resets and Interrupts
Interrupts
4.4.2.2 Break Interrupt
The break module causes the CPU to execute an SWI instruction at a
software-programmable break point.
4.4.2.3 IRQ Pin
A logic 0 on the IRQ1 pin latches an external interrupt request.
4.4.2.4 Internal Clock Generator (ICG)
The ICG can generate a CPU interrupt request every time the selected
internal or external clock becomes inactive. When the clock monitor
CMON bit is set and the currently selected clock becomes inactive, the
clock monitor interrupt flag CMF is set. The clock monitor interrupt
enable bit (CMIE) enables ICG CPU interrupt requests. CMIE, CMF, and
CMON are in the ICGCR control register.
4.4.2.5 Timer Interface Module 1 (TIM1)
TIM1 CPU interrupt sources:
• TIM1 overflow flag (TOF) — The TOF bit is set when the TIM1
counter value rolls over to $0000 after matching the value in the
TIM1 counter modulo registers. The TIM1 overflow interrupt
enable bit, TOIE, enables TIM1 overflow CPU interrupt requests.
TOF and TOIE are in the TIM1 status and control register.
• TIM1 channel flags (CH1F–CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. The
channel x interrupt enable bit, CHxIE, enables channel x
TIM1 CPU interrupt requests. CHxF and CHxIE are in the TIM1
channel x status and control register.
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
MOTOROLA
Resets and Interrupts
Technical Data
81