MC68HC908GT16 Datasheet, PDF (136/412 Pages) Motorola, Inc – Microcontrollers

Internal Clock Generator (ICG) Module
(CGMXCLK, CGMOUT, COPCLK, and TBMCLK) will be held low.
Power consumption will be minimal.
If OSCENINSTOP is high, the ICG is enabled in stop and activity will
continue. This is useful if the timebase module (TBM) is required to bring
the MCU out of stop mode. ICG interrupts will not bring the MCU out of
stop mode in this case.
During stop mode, if OSCENINSTOP is low, several functions in the ICG
are affected. The stable bits (ECGS and ICGS) are cleared, which will
enable the external clock stabilization divider upon recovery. The clock
monitor is disabled (CMON = 0) which will also clear the clock monitor
interrupt enable (CMIE) and clock monitor flag (CMF) bits. The CS,
ICGON, ECGON, N, TRIM, DDIV, and DSTG bits are unaffected.
7.7 CONFIG2 Options
Four CONFIG2 register options affect the functionality of the ICG. These
options are:
1. EXTCLKEN, external clock enable
2. EXTXTALEN, external crystal enable
3. EXTSLOW, slow external clock
4. OSCENINSTOP, oscillator enable in stop
All CONFIG2 options will have a default setting. Refer to
Section 8. Configuration Register (CONFIG) on how the CONFIG2
register is used.
7.7.1 External Clock Enable (EXTCLKEN)
External clock enable (EXTCLKEN), when set, enables the ECGON bit
to be set. ECGON turns on the external clock input path through the
PTE4/OSC1 pin. When EXTCLKEN is clear, ECGON cannot be set and
PTE4/OSC1 will always perform the PTE4 function.
The default state for this option is clear.
Technical Data
136
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
Internal Clock Generator (ICG) Module
MOTOROLA