MC68HC908GT16 Datasheet, PDF (353/412 Pages) Motorola, Inc – Microcontrollers

Timebase Module (TBM)
Timebase Register Description
21.5 Timebase Register Description
The timebase has one register, the timebase control regster (TBCR),
which is used to enable the timebase interrupts and set the rate.
Address: $001C
Bit 7
6
5
4
3
2
1
Bit 0
Read: TBIF
0
TBR2 TBR1 TBR0
TBIE TBON
R
Write:
TACK
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
R = Reserved
Figure 21-2. Timebase Control Register (TBCR)
TBIF — Timebase Interrupt Flag
This read-only flag bit is set when the timebase counter has rolled
over.
1 = Timebase interrupt pending
0 = Timebase interrupt not pending
TBR2:TBR0 — Timebase Rate Selection
These read/write bits are used to select the rate of timebase interrupts
as shown in Table 21-1.
Table 21-1. Timebase Rate Selection for OSC1 = 32.768 kHz
TBR2
0
0
0
0
1
1
1
1
TBR1
0
0
1
1
0
0
1
1
TBR0
0
1
0
1
0
1
0
1
Divider
32768
8192
2048
128
64
32
16
8
Timebase Interrupt Rate
Hz
ms
1
1000
4
250
16
62.5
256
~ 3.9
512
~2
1024
~1
2048
~0.5
4096
~0.24
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
MOTOROLA
Timebase Module (TBM)
Technical Data
353