MC68HC908GT16 Datasheet, PDF (275/412 Pages) Motorola, Inc – Microcontrollers

Enhanced Serial Communications Interface (ESCI) Module
I/O Registers
18.9.2 ESCI Control Register 2
ESCI control register 2 (SCC2):
• Enables these CPU interrupt requests:
– SCTE bit to generate transmitter CPU interrupt requests
– TC bit to generate transmitter CPU interrupt requests
– SCRF bit to generate receiver CPU interrupt requests
– IDLE bit to generate receiver CPU interrupt requests
• Enables the transmitter
• Enables the receiver
• Enables ESCI wakeup
• Transmits ESCI break characters
Address: $0014
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SCTIE TCIE SCRIE ILIE
TE
RE
RWU SBK
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 18-10. ESCI Control Register 2 (SCC2)
SCTIE — ESCI Transmit Interrupt Enable Bit
This read/write bit enables the SCTE bit to generate ESCI transmitter
CPU interrupt requests. Setting the SCTIE bit in SCC2 enables the
SCTE bit to generate CPU interrupt requests. Reset clears the
SCTIE bit.
1 = SCTE enabled to generate CPU interrupt
0 = SCTE not enabled to generate CPU interrupt
TCIE — Transmission Complete Interrupt Enable Bit
This read/write bit enables the TC bit to generate ESCI transmitter
CPU interrupt requests. Reset clears the TCIE bit.
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
MC68HC908GT16 • MC68HC908GT8 — Rev. 2
MOTOROLA
Enhanced Serial Communications Interface (ESCI) Module
Technical Data
275