MC68HC908AS32A Datasheet, PDF (93/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

BDLC CPU Interface
Table 4-5. BDLC Interrupt Sources
BSVR I3 I2 I1 I0
$00 0 0 0 0
$04 0 0 0 1
$08 0 0 1 0
$0C 0 0 1 1
$10 0 1 0 0
$14 0 1 0 1
$18 0 1 1 0
$1C 0 1 1 1
$20 1 0 0 0
Interrupt Source
No interrupts pending
Received EOF
Received IFR byte (RXIFR)
BDLC Rx data register full (RDRF)
BDLC Tx data register empty (TDRE)
Loss of arbitration
Cyclical redundancy check (CRC) error
Symbol invalid or out of range
wakeup
Priority
0 (lowest)
1
2
3
4
5
6
7
8 (highest)
Upon receiving a BDLC interrupt, the user can read the value within the BSVR, transferring it to the CPU’s
index register. The value can then be used to index into a jump table, with entries four bytes apart, to
quickly enter the appropriate service routine. For example:
Service
*
*
JMPTAB
*
LDX BSVR
JMP JMPTAB,X
JMP SERVE0
NOP
JMP SERVE1
NOP
JMP SERVE2
NOP
JMP SERVE8
END
Fetch State Vector Number
Enter service routine,
(must end in RTI)
Service condition #0
Service condition #1
Service condition #2
Service condition #8
NOTE
The NOPs are used only to align the JMPs onto 4-byte boundaries so that
the value in the BSVR can be used intact. Each of the service routines must
end with an RTI instruction to guarantee correct continued operation of the
device. Note also that the first entry can be omitted since it corresponds to
no interrupt occurring.
The service routines should clear all of the sources that are causing the pending interrupts. Note that the
clearing of a high priority interrupt may still leave a lower priority interrupt pending, in which case bits I0,
I1, and I2 of the BSVR will then reflect the source of the remaining interrupt request.
If fewer states are used or if a different software approach is taken, the jump table can be made smaller
or omitted altogether.
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
93