MC68HC908AS32A Datasheet, PDF (92/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Byte Data Link Controller (BDLC)
0 = The TMIFR0 bit will be cleared automatically; once the BDLC has successfully transmitted the
EOD symbol; by the detection of an error on the multiplex bus; or by a transmitter underrun
caused when the programmer does not write another byte to the BDR after the TDRE interrupt.
If the TMIFR0 bit is set, the BDLC will attempt to transmit the normalization symbol followed by the byte
in the BDR. After the byte in the BDR has been loaded into the transmit shift register, a TDRE interrupt
(see 4.6.4 BDLC State Vector Register) will occur similar to the main message transmit sequence. The
programmer should then load the next byte of the IFR into the BDR for transmission. When the last
byte of the IFR has been loaded into the BDR, the programmer should set the TEOD bit in the BCR2.
This will instruct the BDLC to transmit an EOD symbol once the byte in the BDR is transmitted,
indicating the end of the IFR portion of the message frame. The BDLC will not append a CRC when
the TMIFR0 is set.
If the programmer attempts to set the TMIFR0 bit after the EOD symbol has been received from the
bus, the TMIFR0 bit will remain in the reset state, and no attempt will be made to transmit an IFR byte.
If a loss of arbitration occurs when the BDLC is transmitting, the TMIFR0 bit will be cleared and no
attempt will be made to retransmit the byte in the BDR. If loss of arbitration occurs in the last two bits
of the IFR byte, two additional 1 bits (active short bits) will be sent out.
NOTE
The extra logic 1s are an enhancement to the J1850 protocol which forces
a byte boundary condition fault. This is helpful in preventing noise from
going onto the J1850 bus from a corrupted message.
4.6.4 BDLC State Vector Register
This register is provided to substantially decrease the CPU overhead associated with servicing interrupts
while under operation of a multiplex protocol. It provides an index offset that is directly related to the
BDLC’s current state, which can be used with a user-supplied jump table to rapidly enter an interrupt
service routine. This eliminates the need for the user to maintain a duplicate state machine in software.
Address: $003E
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
I3
I2
I1
I0
0
0
Write: R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
R = Reserved
Figure 4-20. BDLC State Vector Register (BSVR)
I0, I1, I2, and I3 — Interrupt Source Bits
These bits indicate the source of the interrupt request that currently is pending. The encoding of these
bits are listed in Table 4-5.
Bits I0, I1, I2, and I3 are cleared by a read of the BSVR except when the BDLC data register needs
servicing (RDRF, RXIFR, or TDRE conditions). RXIFR and RDRF can be cleared only by a read of the
BSVR followed by a read of the BDLC data register (BDR). TDRE can either be cleared by a read of
the BSVR followed by a write to the BDLC BDR or by setting the TEOD bit in BCR2.
MC68HC908AS32A Data Sheet, Rev. 2.0
92
Freescale Semiconductor