MC68HC908AS32A Datasheet, PDF (81/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

BDLC Protocol Handler
ACTIVE
TRANSMITTER A
PASSIVE
ACTIVE
TRANSMITTER B
PASSIVE
ACTIVE
J1850 BUS
PASSIVE
0
1
1
1
TRANSMITTER A DETECTS
AN ACTIVE STATE ON
THE BUS AND STOPS
TRANSMITTING
0
1
1
0
0
0
1
1
TRANSMITTER B WINS
ARBITRATION AND
0
0
CONTINUES
TRANSMITTING
DATA DATA DATA
DATA DATA
SOF
BIT 1 BIT 2 BIT 3
BIT 4 BIT 5
Figure 4-12. J1850 VPW Bitwise Arbitrations
4.5 BDLC Protocol Handler
The protocol handler is responsible for framing, arbitration, CRC generation/checking, and error
detection. The protocol handler conforms to SAE J1850 — Class B Data Communications Network
Interface.
NOTE
Freescale assumes that the reader is familiar with the J1850 specification
before this protocol handler description is read.
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 4-13. BDLC Block Diagram
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
81