MC68HC908AS32A Datasheet, PDF (200/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
Wait mode can also be exited by a reset or break. A break interrupt during wait mode sets the SIM break
wait bit, BW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in the configuration
register is 0, then the computer operating properly module (COP) is enabled and remains active in wait
mode.
IAB
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 15-12. Wait Mode Entry Timing
IAB
$6E0B
$6E0C $00FF $00FE $00FD $00FC
IDB $A6 $A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
Figure 15-13. Wait Recovery from Interrupt or Break
IAB
$6E0B
32
Cycles
32
Cycles
RSTVCTH RSTVCTL
IDB $A6 $A6
$A6
RST
CGMXCLK
Figure 15-14. Wait Recovery from Internal Reset
MC68HC908AS32A Data Sheet, Rev. 2.0
200
Freescale Semiconductor