MC68HC908AS32A Datasheet, PDF (111/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Acquisition/Lock Time Specifications
time varies according to the original error in the output. Minor errors may not even be registered. Typical
PLL applications prefer to use this definition because the system requires the output frequency to be
within a certain tolerance of the desired frequency regardless of the size of the initial error.
The discrepancy in these definitions makes it difficult to specify an acquisition or lock time for a typical
PLL. Therefore, the definitions for acquisition and lock times for this module are:
• Acquisition time, t_ACQ, is the time the PLL takes to reduce the error between the actual output
frequency and the desired output frequency to less than the tracking mode entry tolerance, ∆_TRK.
Acquisition time is based on an initial frequency error, (f_DES – f_ORIG)/f_DES, of not more than ±100%.
In automatic bandwidth control mode (see 5.3.2.3 Manual and Automatic PLL Bandwidth Modes),
acquisition time expires when the ACQ bit becomes set in the PLL bandwidth control register
(PBWC).
• Lock time, t_Lock, is the time the PLL takes to reduce the error between the actual output frequency
and the desired output frequency to less than the lock mode entry tolerance, ∆_Lock. Lock time is
based on an initial frequency error, (f_DES – f_ORIG)/f_DES, of not more than ±100%. In automatic
bandwidth control mode, lock time expires when the LOCK bit becomes set in the PLL bandwidth
control register (PBWC). See 5.3.2.3 Manual and Automatic PLL Bandwidth Modes for more
information.
Obviously, the acquisition and lock times can vary according to how large the frequency error is and may
be shorter or longer in many cases.
5.9.2 Parametric Influences on Reaction Time
Acquisition and lock times are designed to be as short as possible while still providing the highest possible
stability. These reaction times are not constant, however. Many factors directly and indirectly affect the
acquisition time.
The most critical parameter which affects the reaction times of the PLL is the reference frequency,
f_CGMRDV (please reference Figure 5-2). This frequency is the input to the phase detector and controls how
often the PLL makes corrections. For stability, the corrections must be small compared to the desired
frequency, so several corrections are required to reduce the frequency error. Therefore, the slower the
reference the longer it takes to make these corrections. This parameter is also under user control via the
choice of crystal frequency f_CGMXCLK.
Another critical parameter is the external filter capacitor. The PLL modifies the voltage on the VCO by
adding or subtracting charge from this capacitor. Therefore, the rate at which the voltage changes for a
given frequency error (thus a change in charge) is proportional to the capacitor size. The size of the
capacitor also is related to the stability of the PLL. If the capacitor is too small, the PLL cannot make small
enough adjustments to the voltage and the system cannot lock. If the capacitor is too large, the PLL may
not be able to adjust the voltage in a reasonable time. See 5.9.3 Choosing a Filter Capacitor for more
information.
Also important is the operating voltage potential applied to V_DDA. The power supply potential alters the
characteristics of the PLL. A fixed value is best. Variable supplies, such as batteries, are acceptable if
they vary within a known range at very slow speeds. Noise on the power supply is not acceptable,
because it causes small frequency errors which continually change the acquisition time of the PLL.
Temperature and processing also can affect acquisition time because the electrical characteristics of the
PLL change. The part operates as specified as long as these influences stay within the specified limits.
External factors, however, can cause drastic changes in the operation of the PLL. These factors include
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
111