MC68HC908AS32A Datasheet, PDF (248/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

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18.2.2.1 Break Status and Control Register
The break status and control register contains break module enable and status bits.
Address: $FE0E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
BRKE BRKA
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 18-3. Break Status and Control Register (BSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches. Clear BRKE by writing a 0 to bit
7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled on 16-bit address match
BRKA — Break Active Bit
This read/write status and control bit is set when a break address match occurs. Writing a 1 to BRKA
generates a break interrupt. Clear BRKA by writing a 0 to it before exiting the break routine. Reset
clears the BRKA bit.
1 = When read, break address match
0 = When read, no break address match
18.2.2.2 Break Address Registers
The break address registers contain the high and low bytes of the desired breakpoint address. Reset
clears the break address registers.
Register Name and Address
BRKH — $FE0C
Bit 7
6
5
4
3
2
Read:
Bit 15
14
13
12
11
10
Write:
1
Bit 0
9
Bit 8
Reset: 0
0
0
0
0
0
0
0
Register Name and Address
BRKL — $FE0D
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 18-4. Break Address Registers (BRKH and BRKL)
MC68HC908AS32A Data Sheet, Rev. 2.0
248
Freescale Semiconductor