MC68HC908AS32A Datasheet, PDF (77/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

BDLC MUX Interface
End-of-Frame Symbol (EOF)
The EOF symbol is defined as an active-to-passive transition followed by a passive period 280 µs in
length (see Figure 4-7(f)). If no IFR byte is transmitted after an EOD symbol is transmitted, after
another 80 µs the EOD becomes an EOF, indicating completion of the message.
Inter-Frame Separation Symbol (IFS)
The IFS symbol is defined as a passive period 300 µs in length. The 20-µs IFS symbol contains no
transition, since when used it always appends to an EOF symbol (see Figure 4-7(g)).
Idle
An idle is defined as a passive period greater than 300 µs in length.
4.4.4 J1850 VPW Valid/Invalid Bits and Symbols
The timing tolerances for receiving data bits and symbols from the J1850 bus have been defined to allow
for variations in oscillator frequencies. In many cases the maximum time allowed to define a data bit or
symbol is equal to the minimum time allowed to define another data bit or symbol.
Since the minimum resolution of the BDLC for determining what symbol is being received is equal to a
single period of the MUX interface clock (t_BDLC), an apparent separation in these maximum time/minimum
time concurrences equal to one cycle of t_BDLC occurs.
This one clock resolution allows the BDLC to differentiate properly between the different bits and symbols.
This is done without reducing the valid window for receiving bits and symbols from transmitters onto the
J1850 bus which have varying oscillator frequencies.
In Huntsinger’s’ variable pulse width (VPW) modulation bit encoding, the tolerances for both the passive
and active data bits received and the symbols received are defined with no gaps between definitions. For
example, the maximum length of a passive logic 0 is equal to the minimum length of a passive logic 1,
and the maximum length of an active logic 0 is equal to the minimum length of a valid SOF symbol. See
Figure 4-8.
64 µs
200 µs
128 µs
ACTIVE
(1) INVALID PASSIVE BIT
PASSIVE
a
ACTIVE
(2) VALID PASSIVE LOGIC 0
PASSIVE
a
b
ACTIVE
(3) VALID PASSIVE LOGIC 1
PASSIVE
ACTIVE
b
c
(4) VALID EOD SYMBOL
PASSIVE
c
d
Figure 4-8. J1850 VPW Received Passive Symbol Times
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
77