MC68HC908AS32A Datasheet, PDF (74/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Byte Data Link Controller (BDLC)
CRC generation uses the divisor polynomial X⁸ + X⁴ + X³ + X² + 1. The remainder polynomial initially
is set to all ones. Each byte in the message after the start of frame (SOF) symbol is processed serially
through the CRC generation circuitry. The one’s complement of the remainder then becomes the 8-bit
CRC byte, which is appended to the message after the data bytes in MSB-to-LSB order.
When receiving a message, the BDLC uses the same divisor polynomial. All data bytes, excluding the
SOF and end of data symbols (EOD) but including the CRC byte, are used to check the CRC. If the
message is error free, the remainder polynomial will equal X⁷ + X⁶ + X² = $C4, regardless of the data
contained in the message. If the calculated CRC does not equal $C4, the BDLC will recognize this as
a CRC error and set the CRC error flag in the BSVR.
EOD — End-of-Data Symbol
The EOD symbol is a long 200-µs passive period on the J1850 bus used to signify to any recipients of
a message that the transmission by the originator has completed. No flag is set upon reception of the
EOD symbol.
IFR — In-Frame Response Bytes
The IFR section of the J1850 message format is optional. Users desiring further definition of in-frame
response should review the SAE J1850 — Class B Data Communications Network Interface
specification.
EOF — End-of-Frame Symbol
This symbol is a long 280-µs passive period on the J1850 bus and is longer than an end-of-data (EOD)
symbol, which signifies the end of a message. Since an EOF symbol is longer than a 200-µs EOD
symbol, if no response is transmitted after an EOD symbol, it becomes an EOF, and the message is
assumed to be completed. The EOF flag is set upon receiving the EOF symbol.
IFS — Inter-Frame Separation Symbol
The IFS symbol is a 20-µs passive period on the J1850 bus which allows proper synchronization
between nodes during continuous message transmission. The IFS symbol is transmitted by a node
after the completion of the end-of-frame (EOF) period and, therefore, is seen as a 300-µs passive
period.
When the last byte of a message has been transmitted onto the J1850 bus and the EOF symbol time
has expired, all nodes then must wait for the IFS symbol time to expire before transmitting a
start-of-frame (SOF) symbol, marking the beginning of another message.
However, if the BDLC is waiting for the IFS period to expire before beginning a transmission and a
rising edge is detected before the IFS time has expired, it will synchronize internally to that edge. If a
write to the BDR register (for instance, to initiate transmission) occurred on or before 104 • t_BDLC from
the received rising edge, then the BDLC will transmit and arbitrate for the bus. If a CPU write to the
BDR register occurred after 104 • t_BDLC from the detection of the rising edge, then the BDLC will not
transmit, but will wait for the next IFS period to expire before attempting to transmit the byte.
A rising edge may occur during the IFS period because of varying clock tolerances and loading of the
J1850 bus, causing different nodes to observe the completion of the IFS period at different times. To
allow for individual clock tolerances, receivers must synchronize to any SOF occurring during an IFS
period.
NOTE
If two messages are received with a 300 µs (± 1 µs) interframe separation
(IFS) as measured at the RX pin, the start-of-frame (SOF) symbol of the
second message will generate an invalid symbol interrupt. This interrupt
results in the second message being lost and will therefore be unavailable
MC68HC908AS32A Data Sheet, Rev. 2.0
74
Freescale Semiconductor