MC68HC908AS32A Datasheet, PDF (72/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Byte Data Link Controller (BDLC)
4.4.1 Rx Digital Filter
The receiver section of the BDLC includes a digital low-pass filter to remove narrow noise pulses from the
incoming message. An outline of the digital filter is shown in Figure 4-5.
RX DATA
FROM
PHYSICAL
INTERFACE
(BDRXD)
INPUT
SYNC
DQ
4-BIT UP/DOWN COUTER
UP/DOWN
OUT
DATA
LATCH
DQ
FILTERED
RX DATA OUT
MUX
INTERFACE
CLOCK
Figure 4-5. BDLC Rx Digital Filter Block Diagram
4.4.1.1 Operation
The clock for the digital filter is provided by the MUX interface clock (see f_BDLC parameter in Table 4-3).
At each positive edge of the clock signal, the current state of the receiver physical interface (BDRxD)
signal is sampled. The BDRxD signal state is used to determine whether the counter should increment or
decrement at the next negative edge of the clock signal.
The counter will increment if the input data sample is high but decrement if the input sample is low.
Therefore, the counter will thus progress either up toward 15 if, on average, the BDRxD signal remains
high or progress down toward 0 if, on average, the BDRxD signal remains low.
When the counter eventually reaches the value 15, the digital filter decides that the condition of the
BDRxD signal is at a stable logic level 1 and the data latch is set, causing the filtered Rx data signal to
become a logic level 1. Furthermore, the counter is prevented from overflowing and can only be
decremented from this state.
Alternatively, should the counter eventually reach the value 0, the digital filter decides that the condition
of the BDRxD signal is at a stable logic level 0 and the data latch is reset, causing the filtered Rx data
signal to become a logic level 0. Furthermore, the counter is prevented from underflowing and can only
be incremented from this state.
The data latch will retain its value until the counter next reaches the opposite end point, signifying a
definite transition of the signal.
4.4.1.2 Performance
The performance of the digital filter is best described in the time domain rather than the frequency domain.
If the signal on the BDRxD signal transitions, then there will be a delay before that transition appears at
the filtered Rx data output signal. This delay will be between 15 and 16 clock periods, depending on where
the transition occurs with respect to the sampling points. This filter delay must be taken into account when
performing message arbitration.
MC68HC908AS32A Data Sheet, Rev. 2.0
72
Freescale Semiconductor