MC68HC908AS32A Datasheet, PDF (70/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Byte Data Link Controller (BDLC)
4.3.1.1 Power Off Mode
This mode is entered from reset mode whenever the BDLC supply voltage, V_DD, drops below its minimum
specified value for the BDLC to guarantee operation. The BDLC will be placed in reset mode by
low-voltage reset (LVR) before being powered down. In this mode, the pin input and output specifications
are not guaranteed.
4.3.1.2 Reset Mode
This mode is entered from the power off mode whenever the BDLC supply voltage, V_DD, rises above its
minimum specified value (V_DD –10%) and some MCU reset source is asserted. The internal MCU reset
must be asserted while powering up the BDLC or an unknown state will be entered and correct operation
cannot be guaranteed. Reset mode is also entered from any other mode as soon as one of the MCU’s
possible reset sources (such as LVR, POR, COP watchdog, and reset pin, etc.) is asserted.
In reset mode, the internal BDLC voltage references are operative; V_DD is supplied to the internal circuits
which are held in their reset state; and the internal BDLC system clock is running. Registers will assume
their reset condition. Outputs are held in their programmed reset state. Therefore, inputs and network
activity are ignored.
4.3.1.3 Run Mode
This mode is entered from the reset mode after all MCU reset sources are no longer asserted. Run mode
is entered from the BDLC wait mode whenever activity is sensed on the J1850 bus.
Run mode is entered from the BDLC stop mode whenever network activity is sensed, although messages
will not be received properly until the clocks have stabilized and the CPU is in run mode also.
In this mode, normal network operation takes place. The user should ensure that all BDLC transmissions
have ceased before exiting this mode.
4.3.1.4 BDLC Wait Mode
This power-conserving mode is entered automatically from run mode whenever the CPU executes a
WAIT instruction and if the WCM bit in the BCR1 register is cleared previously.
In this mode, the BDLC internal clocks continue to run. The first passive-to-active transition of the bus
generates a CPU interrupt request from the BDLC which wakes up the BDLC and the CPU. In addition,
if the BDLC receives a valid EOF symbol while operating in wait mode, then the BDLC also will generate
a CPU interrupt request which wakes up the BDLC and the CPU. See 4.7.1 Wait Mode.
4.3.1.5 BDLC Stop Mode
This power-conserving mode is entered automatically from run mode whenever the CPU executes a
STOP instruction or if the CPU executes a WAIT instruction and the WCM bit in the BCR1 register is set
previously.
In this mode, the BDLC internal clocks are stopped but the physical interface circuitry is placed in a
low-power mode and awaits network activity. If network activity is sensed, then a CPU interrupt request
will be generated, restarting the BDLC internal clocks. See 4.7.2 Stop Mode.
MC68HC908AS32A Data Sheet, Rev. 2.0
70
Freescale Semiconductor