MC68HC908AS32A Datasheet, PDF (88/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Byte Data Link Controller (BDLC)
WCM — Wait Clock Mode Bit
This bit determines the operation of the BDLC during CPU wait mode. See 4.7.2 Stop Mode and 4.7.1
Wait Mode for more details on its use.
1 = Stop BDLC internal clocks during CPU wait mode
0 = Run BDLC internal clocks during CPU wait mode
4.6.3 BDLC Control Register 2
This register controls transmitter operations of the BDLC. It is recommended that BSET and BCLR
instructions be used to manipulate data in this register to ensure that the register’s content does not
change inadvertently.
Address:
Read:
Write:
Reset:
$003D
Bit 7
6
5
4
3
2
1
ALOOP DLOOP RX4XE NBFS TEOD TSIFR TMIFR1
1
1
0
0
0
0
0
Figure 4-18. BDLC Control Register 2 (BCR2)
Bit 0
TMIFR0
0
ALOOP — Analog Loopback Mode Bit
This bit determines whether the J1850 bus will be driven by the analog physical interface’s final drive
stage. The programmer can use this bit to reset the BDLC state machine to a known state after the
off-chip analog transceiver is placed in loopback mode. When the user clears ALOOP, to indicate that
the off-chip analog transceiver is no longer in loopback mode, the BDLC waits for an EOF symbol
before attempting to transmit.
1 = Input to the analog physical interface’s final drive stage is looped back to the BDLC receiver.
The J1850 bus is not driven.
0 = The J1850 bus will be driven by the BDLC. After the bit is cleared, the BDLC requires the bus
to be idle for a minimum of end-of-frame symbol time (t_TRV4) before message reception or a
minimum of inter-frame symbol time (t_TRV6) before message transmission. See 19.12.1 BDLC
Transmitter VPW Symbol Timings.
DLOOP — Digital Loopback Mode Bit
This bit determines the source to which the digital receive input (BDRxD) is connected and can be used
to isolate bus fault conditions (see Figure 4-14). If a fault condition has been detected on the bus, this
control bit allows the programmer to connect the digital transmit output to the digital receive input. In
this configuration, data sent from the transmit buffer will be reflected back into the receive buffer. If no
faults exist in the BDLC, the fault is in the physical interface block or elsewhere on the J1850 bus.
1 = When set, BDRxD is connected to BDTxD. The BDLC is now in digital loopback mode.
0 = When cleared, BDTxD is not connected to BDRxD. The BDLC is taken out of digital loopback
mode and can now drive the J1850 bus normally.
RX4XE — Receive 4X Enable Bit
This bit determines if the BDLC operates at normal transmit and receive speed (10.4 kbps) or receive
only at 41.6 kbps. This feature is useful for fast download of data into a J1850 node for diagnostic or
factory programming of the node.
1 = When set, the BDLC is put in 4X receive-only operation.
0 = When cleared, the BDLC transmits and receives at 10.4 kbps.
MC68HC908AS32A Data Sheet, Rev. 2.0
88
Freescale Semiconductor