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MC68HC908AS32A Datasheet, PDF (62/280 Pages) Freescale Semiconductor, Inc – Microcontrollers
Analog-to-Digital Converter (ADC)
Conversions will continue until the ADCO bit (ADC status control register, $0038) is cleared. The COCO
bit is set after the first conversion and will stay set for the next several conversions until the next write of
the ADC status and control register or the next read of the ADC data register.
3.3.5 Accuracy and Precision
The conversion process is monotonic and has no missing codes. See 19.7 Analog-to-Digital Converter
(ADC) Characteristics for accuracy information.
3.4 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC
conversion. If the COCO bit is set, an interrupt is generated. The COCO bit is not used as a conversion
complete flag when interrupts are enabled.
3.5 Low-Power Modes
The following subsections describe the low-power modes.
3.5.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC
can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power
down the ADC by setting the ADCH[4:0] bits in the ADC status and control register before executing the
WAIT instruction.
3.5.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted.
ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the
analog circuitry before attempting a new ADC conversion after exiting stop mode.
3.6 I/O Signals
The ADC module has 15 channels that are shared with I/O ports B and D. Refer to 19.7 Analog-to-Digital
Converter (ADC) Characteristics for voltages referenced below.
3.6.1 ADC Analog Power Pin (VDDAREF)/ADC Voltage Reference Pin (VREFH)
The ADC analog portion uses VDDAREF as its power pin. Connect the VDDA/VDDAREF pin to the same
voltage potential as VDD. External filtering may be necessary to ensure clean VDDAREF for good results.
VREFH is the high reference voltage for all analog-to-digital conversions.
NOTE
Route VDDAREF carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package. VDDAREF must be present
for operation of the ADC.
MC68HC908AS32A Data Sheet, Rev. 2.0
62
Freescale Semiconductor