MC68HC908AS32A Datasheet, PDF (202/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
15.7 SIM Registers
The SIM has three memory mapped registers.
15.7.1 SIM Break Status Register
The SIM break status register contains a flag to indicate that a break caused an exit from wait mode.
Address:
Read:
Write:
Reset:
$FE00
Bit 7
6
5
4
3
2
1
Bit 0
BW
R
R
R
R
R
R
R
See Note
0
R
= Reserved
NOTE: Writing a 0 clears BW
Figure 15-17. SIM Break Status Register (SBSR)
BW — SIM Break Wait
This status bit is useful in applications requiring a return to wait mode after exiting from a break
interrupt. Clear BW by writing a 0 to it. Reset clears BW.
1 = Wait mode was exited by break interrupt
0 = Wait mode was not exited by break interrupt
15.7.2 SIM Reset Status Register
The SRSR register contains flags that show the source of the last reset. The status register will
automatically clear after reading SRSR. A power-on reset sets the POR bit and clears all other bits in the
register. All other reset sources set the individual flag bits but do not clear the register. More than one
reset source can be flagged at any time depending on the conditions at the time of the internal or external
reset. For example, the POR and LVI bit can both be set if the power supply has a slow rise time.
Address: $FE01
Bit 7
6
5
4
3
2
Read: POR
PIN
COP
ILOP
ILAD
0
Write:
1
Bit 0
LVI
0
POR: 1
0
0
0
0
0
0
0
= Unimplemented
Figure 15-18. SIM Reset Status Register (SRSR)
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of SRSR
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of SRSR
MC68HC908AS32A Data Sheet, Rev. 2.0
202
Freescale Semiconductor