MC68HC908AS32A Datasheet, PDF (152/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output Ports
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears DDRA[7:0], configuring all port A pins
as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 13-3 shows the port A I/O logic.
READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
DDRAx
WRITE PTA ($0000)
PTAx
PTAx
READ PTA ($0000)
Figure 13-3. Port A I/O Circuit
When bit DDRAx is a 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a 0,
reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 13-1 summarizes the operation of the port A pins.
Table 13-1. Port A Pin Functions
DDRA
Bit
PTA
Bit
I/O Pin
Mode
Accesses to DDRA
Read/Write
0
X
Input, Hi-Z
DDRA[7:0]
1
X
Output
DDRA[7:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
Accesses to PTA
Read
Write
Pin
PTA[7:0]⁽¹⁾
PTA[7:0]
PTA[7:0]⁽¹⁾
MC68HC908AS32A Data Sheet, Rev. 2.0
152
Freescale Semiconductor