MC68HC908AS32A Datasheet, PDF (115/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 6
Configuration Register (CONFIG1)
6.1 Introduction
This section describes the configuration register (CONFIG1), which contains bits that configure these
options:
• Resets caused by the low-voltage inhibit (LVI) module
• Power to the LVI module
• LVI enabled during stop mode
• Stop mode recovery time (32 CGMXCLK cycles or 4096 CGMXCLK cycles)
• Computer operating properly (COP) module
• STOP instruction enable/disable
6.2 Functional Description
The configuration register is a write-once register. Out of reset, the configuration register will read the
default value. Once the register is written, further writes will have no effect until a reset occurs.
NOTE
If the LVI module and the LVI reset signal are enabled, a reset occurs when
V_DD falls to a voltage, LVI_TRIPF. Once an LVI reset occurs, the MCU
remains in reset until V_DD rises to a voltage, LVI_TRIPR.
Address: $001F
Bit 7
6
5
4
3
2
1
Read:
LVISTOP
R
Write:
LVIRST LVIPWR SSREC COPL STOP
Reset: 0
1
1
1
0
0
0
R
= Reserved
Figure 6-1. Configuration Register (CONFIG1)
Bit 0
COPD
0
LVISTOP — LVI Stop Mode Enable Bit
LVISTOP enables the LVI module in stop mode. Refer to Chapter 11 Low-Voltage Inhibit (LVI).
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
NOTE
To have the LVI enabled in stop mode, the LVIPWR must be at a 1 and the
LVISTOP bit must be at a 1. Take note that by enabling the LVI in stop
mode, the stop I_DD current will be higher.
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
115