MC68HC908AS32A Datasheet, PDF (253/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Monitor Module (MON)
18.3.1.3 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
(See Figure 18-7 and Figure 18-8.) The data transmit and receive rate can be anywhere up to 28.8 Kbaud.
Transmit and receive baud rates must be identical.
NEXT
START
START
BIT
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT
BIT
Figure 18-7. Monitor Data Format
$A5
BREAK
START
BIT
START
BIT
NEXT
START
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT
BIT
STOP
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT ^NEXT
START
BIT
Figure 18-8. Sample Monitor Waveforms
18.3.1.4 Break Signal
A start bit followed by nine low bits is a break signal (see Figure 18-9). When the monitor receives a break
signal, it drives the PTA0 pin high for the duration of two bits before echoing the break signal.
MISSING STOP BIT
2-STOP BIT DELAY BEFORE ZERO ECHO
01234567
01234567
Figure 18-9. Break Transaction
18.3.1.5 Baud Rate
With a 4.9152-MHz crystal and the PTC3 pin high during reset, data is transferred between the monitor
and host at 4800 baud. If the PTC3 pin is low during reset, the monitor baud rate is 9600. When the CGM
output, CGMOUT, is driven by the PLL, the baud rate is determined by the MUL[7:4] bits in the PLL
programming register (PPG). See Chapter 5 Clock Generator Module (CGM).
Table 18-3. Monitor Baud Rate Selection
Monitor
Baud Rate
4.9152 MHz
4.194 MHz
1
4800
4096
2
9600
8192
VCO Frequency Multiplier (N)
3
4
5
14,400
19,200
24,000
12,288
16,384
20,480
6
28,800
24,576
CAUTION
Care should be taken when setting the baud rate since incorrect baud rate
setting can result in communications failure.
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
253