MC68HC908AS32A Datasheet, PDF (112/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
noise injected into the PLL through the filter capacitor, filter capacitor leakage, stray impedances on the
circuit board, and even humidity or circuit board contamination.
5.9.3 Choosing a Filter Capacitor
As described in 5.9.2 Parametric Influences on Reaction Time, the external filter capacitor, C_F, is critical
to the stability and reaction time of the PLL. The PLL is also dependent on reference frequency and supply
voltage. The value of the capacitor must, therefore, be chosen with supply potential and reference
frequency in mind. For proper operation, the external filter capacitor must be chosen according to this
equation:
C_F
=
C
Fac
ta
⎛
⎜
⎝
f--_C^----V_G^----DM----D-_R^--A--_D^---_V^--_{⎠⎟⎞}
For acceptable values of C_Fact, (refer to 19.1 Introduction). For the value of V_DDA, choose the voltage
potential at which the MCU is operating. If the power supply is variable, choose a value near the middle
of the range of possible supply values.
This equation does not always yield a commonly available capacitor size, so round to the nearest
available size. If the value is between two different sizes, choose the higher value for better stability.
Choosing the lower size may seem attractive for acquisition time improvement, but the PLL may become
unstable. Also, always choose a capacitor with a tight tolerance (±20% or better) and low dissipation.
5.9.4 Reaction Time Calculation
The actual acquisition and lock times can be calculated using the equations below. These equations yield
nominal values under the following conditions:
• Correct selection of filter capacitor, C_F (see 5.9.3 Choosing a Filter Capacitor for more information).
• Room temperature operation
• Negligible external leakage on CGMXFC
• Negligible noise
The K factor in the equations is derived from internal PLL parameters. K_ACQ is the K factor when the PLL
is configured in acquisition mode, and K_TRK is the K factor when the PLL is configured in tracking mode.
See 5.3.2.2 Acquisition and Tracking Modes for more information.
t_ACQ
=
⎛
⎜
⎝
f--_C^----V_G^----DM----D-_R^--A--_D^---_V^--_{⎠⎟⎞}
⎛
⎝
-K----_A--8-_C----_Q--_⎠⎞
t_AL
=
⎛
⎜
⎝
f--_C^----V_G^----DM----D-_R^--A--_D^---_V^--_{⎠⎟⎞}
⎛
⎝
-K----_T-4--_R----_K--_⎠⎞
t_Lock = t_ACQ + t_AL
NOTE
The inverse proportionality between the lock time and the reference
frequency.
MC68HC908AS32A Data Sheet, Rev. 2.0
112
Freescale Semiconductor