MC68HC908AS32A Datasheet, PDF (69/280 Pages) Freescale Semiconductor, Inc – Microcontrollers

TO CPU
Functional Description
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 4-2. BDLC Block Diagram
4.3.1 BDLC Operating Modes
The BDLC has five main modes of operation which interact with the power supplies, pins, and the
remainder of the MCU as shown in Figure 4-3.
POWER OFF
V_DD ≤ V_DD (MINIMUM)
V_DD > V_DD (MINIMUM) AND
ANY MCU RESET SOURCE ASSERTED
RESET
ANY MCU RESET SOURCE ASSERTED
(FROM ANY MODE)
COP, ILLADDR, PU, RESET, LVR, POR
NO MCU RESET SOURCE ASSERTED
NETWORK ACTIVITY OR
OTHER MCU WAKEUP
RUN
NETWORK ACTIVITY OR
OTHER MCU WAKEUP
BDLC STOP
STOP INSTRUCTION OR
WAIT INSTRUCTION AND WCM = 1
BDLC WAIT
WAIT INSTRUCTION AND WCM = 0
Figure 4-3. BDLC Operating Modes State Diagram
MC68HC908AS32A Data Sheet, Rev. 2.0
Freescale Semiconductor
69